Source profileQuality 93/100Review permissions

aklofas/kicad-happy/skills/emc/SKILL.md

emc

EMC pre-compliance risk analysis for KiCad PCB designs — 18 check categories, 44 rule IDs covering ground planes, decoupling, I/O filtering, switching harmonics, clock routing, differential pair skew, board edge radiation, PDN impedance, return paths, crosstalk, ESD protection, shielding, and magnetic leakage from switching inductors. Produces severity-ranked risk report with pre-compliance test plan. Supports FCC Part 15, CISPR 32, CISPR 25 (automotive), MIL-STD-461G. SPICE-enhanced when availa

Source repository stars
1,009
Declared platforms
0
Static risk flags
1
Last source update
2026-08-20
Source checked
2026-08-25

Decision brief

What it does: where it fits

Automated EMC risk analysis for KiCad PCB designs. Identifies the most common causes of EMC test failures using geometric rule checks, analytical emission formulas, and optional SPICE simulation.

Best for

    Not for

    • Cannot predict absolute emission levels better than ±10-20 dB
    • Cannot account for enclosure effects (shielding, apertures, seams)

    Compatibility matrix

    Platform support, with evidence labels

    PlatformStatusEvidenceWhat to check
    CodexNot declaredNo explicit evidencePortability before use
    Claude CodeNot declaredNo explicit evidencePortability before use
    CursorNot declaredNo explicit evidencePortability before use
    Gemini CLINot declaredNo explicit evidencePortability before use
    Open the compatibility checker

    Installation

    Inspect first. Install second.

    The source command is displayed only when detected. A safe inspection prompt is always available so your agent can explain every action before execution.

    Source-detected install commandSource
    npx skills add https://github.com/aklofas/kicad-happy --skill "skills/emc"
    Safe inspection promptEditorial

    Inspect the Agent Skill "emc" from https://github.com/aklofas/kicad-happy/blob/43dad2327f09e94bfa65ae6e33981b7077ea11b6/skills/emc/SKILL.md at commit 43dad2327f09e94bfa65ae6e33981b7077ea11b6. List every install step, command, network request, credential, file read/write, external action, and rollback step. Explain whether it fits my task. Do not install or execute anything until I approve.

    Workflow

    What the source asks the agent to do

    1. 01

      Workflow

      Pass --analysis-dir analysis/ — the script auto-resolves schematic.json and pcb.json from the manifest's current run, and writes emc.json into the same folder so the manifest tracks it.

      Pass --analysis-dir analysis/ — the script auto-resolves schematic.json and pcb.json from the manifest's current run, and writes emc.json into the same folder so the manifest tracks it.
    2. 02

      Step 1: Run the analyzers

      Review the “Step 1: Run the analyzers” section in the pinned source before continuing.

      Review and apply the “Step 1: Run the analyzers” source section.
    3. 03

      Step 2: Run EMC analysis

      Pass --analysis-dir analysis/ — the script auto-resolves schematic.json and pcb.json from the manifest's current run, and writes emc.json into the same folder so the manifest tracks it.

      Pass --analysis-dir analysis/ — the script auto-resolves schematic.json and pcb.json from the manifest's current run, and writes emc.json into the same folder so the manifest tracks it.
    4. 04

      Step 3: Interpret results

      Read the JSON report and incorporate findings into the design review. Each finding has a severity, rule ID, description, and actionable recommendation. See "Interpreting Results" below.

      Read the JSON report and incorporate findings into the design review. Each finding has a severity, rule ID, description, and actionable recommendation. See "Interpreting Results" below.
    5. 05

      Related Skills

      Handoff guidance: Run the kicad skill's analyzeschematic.py and analyzepcb.py first — this skill consumes their JSON output. Use --full on the PCB analyzer for best results (enables per-track coordinates for ground plane crossing, edge proximity, and return path checks). During…

      Handoff guidance: Run the kicad skill's analyzeschematic.py and analyzepcb.py first — this skill consumes their JSON output. Use --full on the PCB analyzer for best results (enables per-track coordinates for ground plan…

    Permission review

    Static risk signals and limitations

    Runs scripts

    medium · line 29

    The documentation asks the agent to run terminal commands or scripts.

    python3 <kicad-skill-path>/scripts/analyze_schematic.py design.kicad_sch --analysis-dir analysis/

    Runs scripts

    medium · line 30

    The documentation asks the agent to run terminal commands or scripts.

    python3 <kicad-skill-path>/scripts/analyze_pcb.py design.kicad_pcb --full --analysis-dir analysis/

    Evidence record

    Why each signal appears

    EvidenceSourceComputedTestedEditorial
    SignalValueEvidence typeMeaning
    Quality score93/100ComputedDocumentation, specificity, maintenance, and trust rules
    Repository stars1,009SourceRepository attention, not individual Skill quality
    Compatibility0 platformsSourceDeclared in the catalog source record
    Usage guideautomated source guideEditorialGenerated or reviewed according to the visible evidence level

    Pinned source

    Provenance and original SKILL.md

    Repository
    aklofas/kicad-happy
    Skill path
    skills/emc/SKILL.md
    Commit
    43dad2327f09e94bfa65ae6e33981b7077ea11b6
    License
    MIT
    Collected
    2026-08-25
    Default branch
    main
    View the original SKILL.md

    EMC Pre-Compliance Skill

    Automated EMC risk analysis for KiCad PCB designs. Identifies the most common causes of EMC test failures using geometric rule checks, analytical emission formulas, and optional SPICE simulation.

    This is a risk analyzer, not a compliance predictor. It catches ~70% of common EMC design mistakes before fabrication. It cannot guarantee FCC/CISPR compliance — only a calibrated measurement in an accredited lab can do that. But it can reduce the first-spin failure rate from ~50% toward ~20-30%, potentially saving $5K-$50K per avoided board respin.

    Related Skills

    SkillPurpose
    kicadSchematic/PCB analysis — produces the analyzer JSON this skill consumes
    kicad (thermal)Thermal hotspot analysis — MLCC derating and ferrite/inductor overheating findings can amplify EMC decoupling and filter issues (an over-stressed MLCC degrades; a hot ferrite drifts impedance). Worth cross-checking when EMC flags DC-001/DC-002 or EF-001/EF-002.
    spiceSPICE simulation — provides simulator backend for SPICE-enhanced PDN/filter checks

    Handoff guidance: Run the kicad skill's analyze_schematic.py and analyze_pcb.py first — this skill consumes their JSON output. Use --full on the PCB analyzer for best results (enables per-track coordinates for ground plane crossing, edge proximity, and return path checks). During a design review, run EMC analysis after the schematic/PCB analyzers, SPICE simulation, and thermal analysis, then incorporate EMC findings into the report.

    Requirements

    • Python 3.10+ — stdlib only, no pip dependencies
    • Schematic analyzer JSON — from analyze_schematic.py --output
    • PCB analyzer JSON — from analyze_pcb.py --full --output (recommended with --full)
    • SPICE simulator (optional) — ngspice, LTspice, or Xyce for SPICE-enhanced PDN/filter checks. Auto-detected. Without one, analytical models run unchanged.

    Workflow

    Step 1: Run the analyzers

    python3 <kicad-skill-path>/scripts/analyze_schematic.py design.kicad_sch --analysis-dir analysis/
    python3 <kicad-skill-path>/scripts/analyze_pcb.py design.kicad_pcb --full --analysis-dir analysis/
    

    Step 2: Run EMC analysis

    Pass --analysis-dir analysis/ — the script auto-resolves schematic.json and pcb.json from the manifest's current run, and writes emc.json into the same folder so the manifest tracks it.

    # Recommended: auto-resolve inputs from the current run
    python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/
    
    # Equivalent — explicit paths still accepted (and required if you want to
    # point at a non-current run or override one input)
    python3 <skill-path>/scripts/analyze_emc.py \
        --schematic analysis/<run_id>/schematic.json \
        --pcb analysis/<run_id>/pcb.json \
        --analysis-dir analysis/
    
    # One-off JSON (bypasses the cache)
    python3 <skill-path>/scripts/analyze_emc.py --schematic schematic.json --pcb pcb.json --output emc.json
    
    # SPICE-enhanced (improved PDN and filter accuracy)
    python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --spice-enhanced
    
    # Select target standard
    python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --standard cispr-class-b
    
    # Select target market (sets all applicable standards)
    python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --market eu
    
    # Filter by severity
    python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --severity high
    
    # Human-readable text output
    python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --text
    

    Step 3: Interpret results

    Read the JSON report and incorporate findings into the design review. Each finding has a severity, rule ID, description, and actionable recommendation. See "Interpreting Results" below.

    What Gets Checked

    44 rule IDs across 18 categories. Each rule has a specific threshold, rationale, and source citation — see references/pcb-emc-rules.md for full details.

    CategoryRulesWhat it detects
    Ground planeGP-001 to GP-005Signal crossing voids, zone fragmentation, missing ground planes, low fill ratio, multiple ground domains
    DecouplingDC-001 to DC-003Cap too far from IC, IC with no decoupling cap, cap too far from via
    I/O filteringIO-001, IO-002Connector without filtering, insufficient ground pins
    Switching EMCSW-001 to SW-003Harmonic overlap, switching node copper area, input cap loop area
    Clock routingCK-001 to CK-003Clock on outer layer, long trace, clock near connector
    Via stitchingVS-001Ground via spacing exceeds λ/20 at highest frequency
    StackupSU-001 to SU-003Adjacent signal layers, signal far from reference plane, thin interplane capacitance
    Diff pairDP-001 to DP-004Intra-pair skew vs protocol limits, CM radiation, reference plane change, outer layer routing
    Board edgeBE-001 to BE-003Signal near edge, incomplete ground pour ring, connector area stitching
    PDN impedancePD-001 to PD-004Anti-resonance peaks, distributed rail impedance at IC load points, cross-rail coupling from downstream switching regulators
    Return pathRP-001Layer transition via without nearby ground stitching via
    CrosstalkXT-0013H spacing violation, aggressor-victim pairs
    EMI filterEF-001, EF-002Filter cutoff too close to switching frequency (analytical or SPICE insertion loss)
    ESD pathES-001, ES-002TVS too far from connector, insufficient ground vias near TVS
    Thermal-EMCTH-001, TH-002MLCC DC bias derating (SRF shift), ferrite near heat source
    ShieldingSH-001Connector aperture slot resonance near emission source
    Emission estimatesEE-001, EE-002Board cavity resonance, switching harmonic envelope

    Advisory outputs (not findings):

    • Pre-compliance test plan — frequency band prioritization, interface risk ranking, near-field probe points
    • Regulatory coverage — market-to-standards mapping, coverage matrix (what the tool checks vs what requires lab testing)

    Output Format

    {
      "summary": {
        "total_checks": 42,
        "critical": 2, "high": 5, "medium": 8, "low": 12, "info": 15,
        "emc_risk_score": 73
      },
      "target_standard": "fcc-class-b",
      "findings": [
        {
          "category": "ground_plane",
          "severity": "CRITICAL",
          "rule_id": "GP-001",
          "title": "Signal crosses ground plane void",
          "description": "Net SPI_CLK crosses a 3.2mm gap in GND on In1.Cu",
          "components": ["U3", "U7"],
          "nets": ["SPI_CLK"],
          "recommendation": "Route around the gap, or fill the void"
        }
      ],
      "per_net_scores": [
        {"net": "SPI_CLK", "score": 67, "finding_count": 3, "rules": ["GP-001", "CK-001", "BE-001"]}
      ],
      "test_plan": {
        "frequency_bands": [{"band": "30-88 MHz", "risk_level": "high", "source_count": 12}],
        "interface_risks": [{"connector": "J1", "protocol": "USB", "risk_score": 8}],
        "probe_points": [{"ref": "L1", "x": 45.2, "y": 32.1, "reason": "switching inductor"}]
      },
      "regulatory_coverage": {
        "market": "us",
        "applicable_standards": ["FCC Part 15 Class B"],
        "coverage_matrix": [{"standard": "...", "coverage": "partial", "note": "..."}]
      }
    }
    

    Severity Levels

    SeverityMeaningAction
    CRITICALAlmost certain to cause EMC failureMust fix before fabrication
    HIGHVery likely to cause issuesStrongly recommend fixing
    MEDIUMMay cause issues depending on specificsReview and assess
    LOWMinor risk, good practiceFix if convenient
    INFOInformational — frequencies, estimatesUseful for lab prep

    Risk Score

    Each rule ID contributes at most 3 findings to the score (worst severity first). This prevents per-net rules like GP-001 from saturating the score on 2-layer boards. All findings are still reported — only the score is capped.

    penalty = sum(worst 3 per rule × severity weight), score = max(0, 100 - penalty). Scores below 50 indicate significant EMC risk.

    Interpreting Results

    Ground plane findings — Any CRITICAL finding (signal crossing a void) is almost always a real problem. Fix unconditionally.

    Decoupling findings — Distance-based findings have moderate false positive rates. A cap at 6mm may be fine for a low-speed IC but problematic for a 100MHz clock buffer. Use frequency context to prioritize.

    I/O filtering — Highly relevant for cable-connected products. For board-to-board connections inside an enclosure, the risk is lower.

    Diff pair findings — Protocol-specific skew limits are well-defined. USB HS (25ps), PCIe (5ps), Ethernet (50ps). Findings exceeding these limits are real issues.

    PDN findings — Anti-resonance peaks are real and cause voltage droop. SPICE-verified findings are more accurate than analytical. If a peak is flagged, add a capacitor with SRF near the peak frequency.

    Emission estimates — Order-of-magnitude estimates (±10-20 dB). Use them to prioritize frequency bands for pre-compliance testing, not to predict pass/fail.

    EMC Standards

    StandardFlagUse Case
    FCC Part 15 Class Bfcc-class-bUS residential (default)
    FCC Part 15 Class Afcc-class-aUS commercial/industrial
    CISPR 32 Class Bcispr-class-bInternational (EU CE marking)
    CISPR 32 Class Acispr-class-aInternational commercial
    CISPR 25 Class 5cispr-25Automotive (strictest)
    MIL-STD-461G RE102mil-std-461Military/defense

    The --market flag maps markets to all applicable standards: us, eu, automotive, medical, military.

    Limitations

    • Cannot predict absolute emission levels better than ±10-20 dB
    • Cannot account for enclosure effects (shielding, apertures, seams)
    • Cannot predict cable radiation without knowing external cable routing
    • Cannot replace full-wave simulation for complex geometries
    • Cannot guarantee compliance — only accredited lab measurement can

    Frequently asked questions

    What to verify before installation and use

    What does the emc source document cover?

    Automated EMC risk analysis for KiCad PCB designs. Identifies the most common causes of EMC test failures using geometric rule checks, analytical emission formulas, and optional SPICE simulation.

    How do I install emc?

    The source record exposes this install command: npx skills add https://github.com/aklofas/kicad-happy --skill "skills/emc". Inspect the command and pinned source before running it.

    Which permission-related actions were detected?

    Static rules flagged exec-script in the source; the page lists the matching lines and excerpts.

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